A lithography process that is used to manufacture a semiconductor device, etc., includes forming the pattern of an upper layer by using a pattern (e.g., an overlay mark) formed beforehand in a wafer or the like as a reference to perform a high-precision alignment. The overlay precision of the pattern affects the characteristics of the device that is manufactured. Therefore, after performing the lithography process, the overlay error of the pattern is measured and fed back to the lithography process.
The overlay error of the pattern is measured by measuring a position of a dedicated pattern having dimensions that are different from those of a normal circuit pattern. Higher-precision measuring of such a pattern is possible by using a scanning electron microscope that has a resolution that is higher than that of an optical microscope. It is important to further increase the precision of the measurement of the pattern using the scanning electron microscope.